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A Processor Accelerator for Software Decoding of BCH Codes
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A
No. 7 ;
pp. 1329-1337
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
error correction code, BCH, accelerator, pipelining, | | | Summary | Full Text:PDF | |
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Recent Progress in Forward Error Correction for Optical Communication Systems
Takashi MIZUOCHI | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2005/05/01
Vol. E88-B
No. 5 ;
pp. 1934-1946
Type of Manuscript:
INVITED PAPER (Joint Special Section on Recent Progress in Optoelectronics and Communications)
Category:
Keyword:
optical communications, forward error correction, block turbo code, Reed-Solomon, BCH, concatenated code, product code, iterative decoding, Shannon limit, code rate, | | | Summary | Full Text:PDF | |
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