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IEICE Trans

Keyword : ASIP design

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1161-1173
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
address generation unit (AGU), reconfigurable architecture, ASIP design, architecture exploration, 
 Summary | Full Text:PDF