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IEICE Trans

Keyword : 0.5-V 5T-cell SRAM array

0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell
Khaja Ahmad SHAIK Kiyoo ITOH Amara AMARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/02/01
Vol. E99-A  No. 2 ; pp. 523-530
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
0.5-V 5T-cell SRAM array, multi-divided open bit-lines, boosted word-line, mid-point sensing, 
 Summary | Full Text:PDF