Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A
No. 12 ;
pp. 2538-2544
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
simple disjunctive decomposition, symmetric variables, ordered binary decision diagram, multi-level logic circuit, |