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IEICE Trans

Keyword :  aliasing probability

Parallel Architecture for Generalized LFSR in LSI Built-In Self Testing
Tomoko K. MATSUSHIMA Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1252-1261
Type of Manuscript:  PAPER
Category: Reliability and Fault Analysis
Keyword: 
built-in self test, signature analysis, linear feedback shift register,  aliasing probability, parallel architecture, 
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