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IEICE Trans

Zvi ROTH

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
Fara ASHIKIN Masaki HASHIZUME Hiroyuki YOTSUYANAGI Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/08/01
Vol. E101-D  No. 8  pp. 2053-2063
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
3D stacked IC, open defects, design-for-testability, through-silicon via, electrical interconnect test, 
 Summary | Full Text:PDF
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11  pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical test, built-in test circuit, open defect, interconnect test, design for testability, 
 Summary | Full Text:PDF