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IEICE Trans

Yuya USHIODA

ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
Yuya USHIODA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/03/01
Vol. E107-A  No. 3  pp. 600-609
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Technology and CAD
Keyword: 
adiabatic logic, 2LAL, optimization, decompute operation, 
 Summary | Full Text:PDF