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IEICE Trans

Yutaka OHNO

Operation Speed Consideration of Resonant Tunneling Logic Gate Based on Circuit Simulation
Yutaka OHNO Shigeru KISHIMOTO Takashi MIZUTANI Koichi MAEZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/11/25
Vol. E79-C  No. 11  pp. 1530-1536
Type of Manuscript:  Special Section PAPER (Special Issue on Quantum Effect Devices and Their Fabrication Technologies)
Category: 
Keyword: 
resonant tunneling transistor, MOBILE, operation speed, negative differential resistance, capacitance, 
 Summary | Full Text:PDF