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IEICE Trans

Yusuke YANO

Extraction of Difference in Parasitic Impedance of Electrical and Electronic Devices Mounted on Different Printed Circuit Boards
Yusuke YANO Yoshika IWAOKA Jianqing WANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2026/03/01
Vol. E109-B  No. 3  pp. 449-456
Type of Manuscript:  PAPER
Category: Electromagnetic Compatibility(EMC)
Keyword: 
ABCD parameters, common mode chokes, electromagnetic compatibility, parasitic impedance extraction, simulated annealing, 
 Summary | Full Text:PDF
Approaches to Quantify and Suppress Noise and Improve Signal Integrity in Wearable Wireless Biosignal Systems
Jianqing WANG Yusuke YANO Lijia LIU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2025/09/01
Vol. E108-B  No. 9  pp. 974-982
Type of Manuscript:  INVITED PAPER (Special Section on Electromagnetic Compatibility in Conjunction with EMC Japan/APEMC Okinawa)
Category: 
Keyword: 
wearable device, biosignal sensor, human body communication, EMI, signal integrity, 
 Summary | Full Text:PDF
Equivalent Circuit Model for Simulating ESD Discharge Current in ESD Damage Test
Yusuke YANO Shoma ISHIHARA Hironori ITO Jianqing WANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2025/09/01
Vol. E108-B  No. 9  pp. 1006-1014
Type of Manuscript:  Special Section PAPER (Special Section on Electromagnetic Compatibility in Conjunction with EMC Japan/APEMC Okinawa)
Category: 
Keyword: 
automotive Ethernet, common mode choke, ESD suppression device, ESD damage test, SPICE simulation, 
 Summary | Full Text:PDF
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices
Yusuke YANO Kengo IOKIBE Toshiaki TESHIMA Yoshitaka TOYOTA Toshihiro KATASHITA Yohei HORI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2021/02/01
Vol. E104-B  No. 2  pp. 178-186
Type of Manuscript:  PAPER
Category: Electromagnetic Compatibility(EMC)
Keyword: 
side-channel attack, dynamic current consumption simulation, EMC macro-model, RTL simulation, FPGA, cryptographic device, 
 Summary | Full Text:PDF