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IEICE Trans

Yusuke TSUGITA

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs
Yusuke TSUGITA Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6  pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digital circuits, threshold voltage variation, compensation circuit, PVT variation, 
 Summary | Full Text:PDF