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IEICE Trans

Yuichi SEKIYA

The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit
Ryoichi MIYAUCHI Akio YOSHIDA Shuya NAKANO Hiroki TAMURA Koichi TANNO Yutaka FUKUCHI Yukio KAWAMURA Yuki KODAMA Yuichi SEKIYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2021/08/01
Vol. E104-D  No. 8  pp. 1146-1153
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Circuit Technologies
Keyword: 
all digital frequency locked loop, fractional-N, PVT variation, microcontroller unit, 
 Summary | Full Text:PDF