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IEICE Trans

Youngsoo SOHN

Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications
In-Young CHUNG Youngsoo SOHN Wonki PARK Changhyun KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 753-759
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DLL, jitter, counter, hysteresis, compensation, power noise, glitch, 
 Summary | Full Text:PDF