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IEICE Trans

Yoshito NISHIMICHI

The Performance Evaluation of a 64 b Microprocessor with a Two-Level Cache
Ryuichi YAMAGUCHI Joel BONEY Douglas DUSCHATKO Tetsuya TANAKA Jiro MIYAKE Yoshito NISHIMICHI Hisakazu EDAMATSU Shigeru WATARI Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Vol. E74-C  No. 11  pp. 3803-3809
Type of Manuscript:  Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: System VLSI
Keyword: 
 Summary | Full Text:PDF