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IEICE Trans

Yoshio HIROSE

A VLSI Processor Architecture for a Back-Propagation Accelerator
Yoshio HIROSE Hideaki ANBUTSU Koichi YAMASHITA Gensuke GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1223-1231
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: Application Specific Processors
Keyword: 
back-propagation, gate array, neural network, pipeline, processor, 
 Summary | Full Text:PDF