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IEICE Trans

Yoshihiko YAMAMOTO

Design of the Basic Cell and Metallized RAM for 0.5 µm CMOS Gate Array
Yoji NISHIO Hideo HARA Masahiro IWAMURA Yasuo KAMINAGA Katsunori KOIKE Kosaku HIROSE Takayuki NOTO Satoshi OGUCHI Yoshihiko YAMAMOTO Takeshi ONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1255-1262
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
gate array, basic cell, compiled RAM, metallized RAM, 
 Summary | Full Text:PDF