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IEICE Trans

Yoichi MIYAI

Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement
Hideyuki FUKUHARA Takao KOMATSUZAKI Katsushi BOKU Yoichi MIYAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 852-857
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
yield, random logic circuitry, defect, Monte Calro simulation, 
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