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IEICE Trans

Yohei NAKATA

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme
Go MATSUKAWA Yohei NAKATA Yasuo SUGURE Shigeru OHO Yuta KIMI Masafumi SHIMOZAWA Shuhei YOSHIDA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4  pp. 333-339
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
dual modular redundancy, checkpoint recovery, fault-tolerance, 
 Summary | Full Text:PDF
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4  pp. 332-341
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustness, cache, variation tolerance, 7T/14T SRAM, 
 Summary | Full Text:PDF
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM
Jinwook JUNG Yohei NAKATA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 528-537
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-voltage adaptive cache design, reconfiguring associativity, dynamic voltage frequency scaling, 7T/14T SRAM, 
 Summary | Full Text:PDF
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 523-533
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
network-on-chip, process variation, adaptive circuits, routing algorithm, 
 Summary | Full Text:PDF
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Shunsuke OKUMURA Yuki KAGIYAMA Yohei NAKATA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2693-2700
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
SRAM DMA, transactional memory, checkpoint and recovery, multi-core processor, 
 Summary | Full Text:PDF