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IEICE Trans

Yo-Hao TU

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
Yo-Hao TU Jen-Chieh LIU Kuo-Hsing CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 655-658
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
static-phase-error, delay-locked-loop, frequency multiplier, edge-combiner, time amplifier, 
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