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IEICE Trans

Yihan ZHU

Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM
Yihan ZHU Takashi OHSAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2024/12/01
Vol. E107-C  No. 12  pp. 545-556
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
in-memory computing, binarized neural network (BNN), loadless 4T SRAM, time-multiplexed XNOR multiplier, current sensing scheme, MNIST dataset, 
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