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IEICE Trans

Yi-Cih WU

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs
Shen-Li CHEN Yu-Ting HUANG Yi-Cih WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/05/01
Vol. E100-C  No. 5  pp. 446-452
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
electrostatic discharge (ESD), holding voltage (Vh), P-channel lateral-diffused metal-oxide-semiconductor (pLDMOS), secondary breakdown current (It2), transmission-line pulse (TLP), trigger voltage (Vt1), 
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