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IEICE Trans

Yeonbok LEE

An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging
Yeonbok LEE Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/07/01
Vol. E94-A  No. 7  pp. 1519-1529
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
post-silicon debugging, high-level design, I/O sequence mapping, 
 Summary | Full Text:PDF