IEICE Trans

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IEICE Trans

Yasuaki NISHITANI

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits Takashi HIRAYAMA Rin SUZUKI Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2024/08/01 Vol. E107-D No. 8 pp. 940-948 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Keyword: reversible logic circuits, Toffoli gates, lower bound, logic minimization,
	Summary \| Full Text:PDF

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units Md Belayet ALI Takashi HIRAYAMA Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2231-2243 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: reversible function, reversible adder/subtractor, reversible arithmetic logic unit, incompletely-specified function, operation assignment, quantum cost, multiple-control Toffoli,
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A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits Takashi HIRAYAMA Hayato SUGAWARA Katsuhisa YAMANAKA Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2253-2261 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Reversible/Quantum Computing Keyword: reversible logic circuits, Toffoli gates, lower bound, logic minimization,
	Summary \| Full Text:PDF

The Firing Squad Synchronization Problems for Number Patterns on a Seven-Segment Display and Segment Arrays Kazuya YAMASHITA Mitsuru SAKAI Sadaki HIROSE Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 pp. 3276-3283 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: firing squad synchronization problem, cellular automaton, seven-segment display, segment tree, segment array,
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A Faster Algorithm of Minimizing AND-EXOR Expressions Takashi HIRAYAMA Yasuaki NISHITANI Toru SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2708-2714 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: AND-EXOR two-level circuit, AND-EXOR expression, exclusive-or sum-of-products expression, logic minimization algorithm,
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Secure Multi-Party Computation over Networks Yasuaki NISHITANI Yoshihide IGARASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/03/25 Vol. E83-D No. 3 pp. 561-569 Type of Manuscript: INVITED SURVEY PAPER Category: Parallel and Distributed Algorithms Keyword: security, secure protocols, multi-party computation, cryptography,
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Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/09/25 Vol. E82-D No. 9 pp. 1278-1286 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: logic synthesis, exclusive-or, single stuck-at fault, easily testable realization,
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Some Modifications of the Tournament Algorithm for the Mutual Exclusion Problem Yoshihide IGARASHI Hironobu KURUMAZAKI Yasuaki NISHITANI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/02/25 Vol. E82-D No. 2 pp. 368-375 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: asynchronous processes, concurrency, distributed system, lockout-freedom, mutual exclusion, shared memory,
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Minimization of AND-EXOR Expressions for Symmetric Functions Takashi HIRAYAMA Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 pp. 567-570 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: logic synthesis, AND-EXOR expression, symmetric function, logic minimization algorithm,
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Embeddings of Hyper-Rings in Hypercubes Yukihiro HAMADA Aohan MEI Yasuaki NISHITANI Yoshihide IGARASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/11/25 Vol. E78-A No. 11 pp. 1606-1613 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: hyper-ring, hypercube, embedding, dilation, congestion,
	Summary \| Full Text:PDF

Lower Bounds on Size of Periodic Functions in Exclusive-OR Sum-of-Products Expressions Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/03/25 Vol. E77-A No. 3 pp. 475-482 Type of Manuscript: Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems) Category: Computer Aided Design (CAD) Keyword: exclusive-OR sum-of-products, size of circuits, lower bound, logic minimization, logic design,
	Summary \| Full Text:PDF

Multilevel Network Design for Parity Functions with MOS Cells under Limitations on the Number of Series Transistors Yasuaki NISHITANI Kensuke SHIMIZU
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/08/25 Vol. E71-E No. 8 pp. 791-798 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword:
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