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IEICE Trans

Yang-Shan TONG

An Enhanced BSA for Floorplanning
Jyh Perng FANG Yang-Shan TONG Sao Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 528-534
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
floorplanning, buffer insertion, routing, dominant wide bus, 
 Summary | Full Text:PDF