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| Wenlun ZHANG
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A Cache Memory with 3-Level Tile-Based Data Layout and Tag-Memory Optimization Method for 2-D Data Access
Baokang WANG Min YU Wenlun ZHANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/12/01
Vol. E108-A
No. 12
pp. 1612-1619
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
cache memory, tile/line, recursive data layout, | | | Summary | Full Text:PDF | |
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Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide
Wenlun ZHANG Baokang WANG | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2021/08/01
Vol. E104-C
No. 8
pp. 379-385
Type of Manuscript:
PAPER
Category: Semiconductor Materials and Devices
Keyword:
JLFET, TCAD, GIDL, BTBT, GAA transistor, | | | Summary | Full Text:PDF | |
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