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IEICE Trans

Weixiang SHEN

Low Power Gated Clock Tree Driven Placement
Weixiang SHEN Yici CAI Xianlong HONG Jiang HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 595-603
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
gated clock tree, activity-aware, register placement, 
 Summary | Full Text:PDF