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IEICE Trans

Tzu-Chao LIN

A 30 V High Voltage NMOS Structure Design in Standard 5 V CMOS Processes
Tzu-Chao LIN Jiin-Chuan WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/11/01
Vol. E86-C  No. 11  pp. 2341-2345
Type of Manuscript:  LETTER
Category: Semiconductor Materials and Devices
Keyword: 
standard CMOS processes, high voltage NMOS, breakdown voltage, 
 Summary | Full Text:PDF
Implementing Compensation Capacitor in Logic CMOS Processes
Tzu-Chao LIN Jiin-Chuan WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1642-1650
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
anti-parallel connected PMOS capacitors, accumulation MOSFET (AMOS), Miller compensation, two-stage amplifier, 
 Summary | Full Text:PDF