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IEICE Trans

Tsuneo INABA

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAM, power dissipation, reliability, bit-line, wordline, small swing, threshold voltage, sense amplifier, memory cell, 
 Summary | Full Text:PDF