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IEICE Trans

Tomoya KITAI

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11  pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verification, failure analysis, timed circuits, timing constraints, 
 Summary | Full Text:PDF
Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Tomoya KITAI Yusuke OGURO Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2601-2611
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
Level-oriented model, timed asynchronous circuits, formal verification, time Petri nets, 
 Summary | Full Text:PDF