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IEICE Trans

Tetsuya ICHIKAWA

Leakage Analysis of DPA Countermeasures at the Logic Level
Minoru SAEKI Daisuke SUZUKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 169-178
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacks, differential power analysis, hardware countermeasure, CMOS logic circuit, second-order DPA, 
 Summary | Full Text:PDF
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
Daisuke SUZUKI Minoru SAEKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1  pp. 160-168
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacks, differential power analysis, hardware countermeasure, second-order DPA random switching logic, CMOS logic circuit, 
 Summary | Full Text:PDF
The 128-Bit Block Cipher Camellia
Kazumaro AOKI Tetsuya ICHIKAWA Masayuki KANDA Mitsuru MATSUI Shiho MORIAI Junko NAKAJIMA Toshio TOKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1  pp. 11-24
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
block cipher, block cipher design, cryptanalysis, Camellia, 
 Summary | Full Text:PDF