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IEICE Trans

Tetsuji SUMIOKA

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7  pp. 811-816
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generation, multiple stuck-at fault, vector pair analysis, combinational circuit, 
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