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IEICE Trans

Tatsuya KAWAMOTO

An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach
Tatsuya KAWAMOTO Xin ZHOU Jacir L. BORDIM Yasuaki ITO Koji NAKANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2901-2910
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
multiple-length-numbers, multiple-length-arithmetic, FPGA, RSA, montgomery modular multiplication, 
 Summary | Full Text:PDF