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IEICE Trans

Takuya YASUI

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2746-2755
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Clock Scheduling
Keyword: 
clock scheduling, clock tree synthesis, high-speed, low power, 
 Summary | Full Text:PDF
A Practical Clock Tree Synthesis for Semi-Synchronous Circuits
Keiichi KUROKAWA Takuya YASUI Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2705-2713
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout
Keyword: 
semi-synchronous circuit, clock scheduling, environmental and manufacturing conditions, zero skew clock tree, various timing clock tree, 
 Summary | Full Text:PDF