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IEICE Trans

Takehiro HASEGAWA

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAM, cascade, NAND, folded bitline, open bitline, die size, noise immunity, 
 Summary | Full Text:PDF