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IEICE Trans

Takaaki MINAMI

Estimation of Yield Suppression for 1.5 V-1 Gbit DRAMs Caused by Threshold Voltage Variation of MOSFET due to Microscopic Fluctuation in Dopant Distributions
Shigeyoshi WATANABE Takaaki MINAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/02/25
Vol. E77-C  No. 2  pp. 273-279
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
1 Gbit DRAM, 1.5 V, yield, threshold voltage variation, redundancy, 
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