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IEICE Trans

Tadayuki ICHIHASHI

An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field
Hiromitsu AWANO Tadayuki ICHIHASHI Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/01/01
Vol. E102-A  No. 1  pp. 56-64
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
pairing based cryptography, hardware security, ASIC, optimal-ate pairing, instruction scheduling optimization, 
 Summary | Full Text:PDF