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IEICE Trans

Sunao TORII

An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems
Toshiaki INOUE Takashi MANABE Sunao TORII Satoshi MATSUSHITA Masato EDAHIRO Naoki NISHI Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/08/01
Vol. E84-C  No. 8  pp. 1014-1020
Type of Manuscript:  INVITED PAPER (Special Issue on Silicon Nanodevices)
Category: 
Keyword: 
SIMD, multiplier, embedded microprocessor, on-chip multiprocessor, area-efficiency, 
 Summary | Full Text:PDF