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IEICE Trans

Shunichi NAKAYAMA

An Efficient Algorithm for Multiple Folded Gate Matrix Layout
Shoichiro YAMADA Shunichi NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10  pp. 1645-1651
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
gate matrix layout, folding, module generator, multi-way mini-cut, polar graph, 
 Summary | Full Text:PDF