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IEICE Trans

Shuichi SAKAI

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA
Reoma MATSUO Toru KOIZUMI Hidetsugu IRIE Shuichi SAKAI Ryota SHIOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2025/06/01
Vol. E108-D  No. 6  pp. 558-569
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
GPU, microarchitecture, instruction-level parallelism, out-of-order execution, energy efficiency, 
 Summary | Full Text:PDF
A Principal Factor of Performance in Decoupled Front-End
Yuya DEGAWA Toru KOIZUMI Tomoki NAKAMURA Ryota SHIOYA Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1960-1968
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
instruction fetch, modeling techniques, 
 Summary | Full Text:PDF
FPGA-based Garbling Accelerator with Parallel Pipeline Processing
Rin OISHI Junichiro KADOMOTO Hidetsugu IRIE Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1988-1996
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
secure function evaluation, garbled circuit, FPGA, 
 Summary | Full Text:PDF
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/04/01
Vol. E100-D  No. 4  pp. 822-837
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
superscalar processor, register file, multibanking, 
 Summary | Full Text:PDF
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
Junji YAMADA Ushio JIMBO Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/03/01
Vol. E100-C  No. 3  pp. 232-244
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
register file, register cache, digital design, freePDK, 
 Summary | Full Text:PDF
An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation point, sampling simulation, microarchitecture, processor architecture, simulation, computer architecture, 
 Summary | Full Text:PDF
Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7  pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architecture, load-store queue, bloom filter, low-energy technologies, 
 Summary | Full Text:PDF
Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2  pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecture, register indirect jump, object-oriented programming, 
 Summary | Full Text:PDF
Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1  pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecture, tagged architecture, information security, information flow tracking, 
 Summary | Full Text:PDF
Ultra Dependable Processor
Shuichi SAKAI Masahiro GOSHIMA Hidetsugu IRIE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9  pp. 1386-1393
Type of Manuscript:  INVITED PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
microprocessor architecture, dependable computing, attacks, faults, errors, failures, soft errors, timing errors, tamper resistance, information flow, injection attack, dependability manager, 
 Summary | Full Text:PDF
Processor Pipeline Design for Fast Network Message Handling in RWC-1 Multiprocessor
Hiroshi MATSUOKA Kazuaki OKAMOTO Hideo HIRONO Mitsuhisa SATO Takashi YOKOTA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1391-1397
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
massively parallel computer, loosely coupled multiprocessor, multi-threaded execution, super-scalar processor, processor pipeline, 
 Summary | Full Text:PDF
hMDCE: The Hierarchical Multidimensional Directed Cycles Ensemble Network
Takashi YOKOTA Hiroshi MATSUOKA Kazuaki OKAMOTO Hideo HIRONO Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1099-1106
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
interconnection networks, hierarchical networks, routing algorithms, performance evaluation, massively parallel computers, multithreaded architecture, 
 Summary | Full Text:PDF
Message-Based Efficient Remote Memory Access on a Highly Parallel Computer EM-X
Yuetsu KODAMA Hirohumi SAKANE Mitsuhisa SATO Hayato YAMANA Shuichi SAKAI Yoshinori YAMAGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1065-1071
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Architectures
Keyword: 
Fine grain communication, multithread architecture, distributed shared memory, 
 Summary | Full Text:PDF
Synchronization Mechanisms of a Highly Parallel Dataflow Machine EM-4
Yoshinori YAMAGUCHI Shuichi SAKAI Yuetsu KODAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1991/01/25
Vol. E74-D  No. 1  pp. 204-213
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
 Summary | Full Text:PDF