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IEICE Trans

Shotaro SUGIYAMA

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor
Shotaro SUGIYAMA Hiromitsu AWANO Makoto IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2290-2296
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ECDSA, V2X communication, Hardware security, ASIC, scalar multiplication, 
 Summary | Full Text:PDF