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IEICE Trans

Shintaro YAMAMICHI

A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect
Yoichiro KURITA Koji SOEJIMA Katsumi KIKUCHI Masatake TAKAHASHI Masamoto TAGO Masahiro KOIKE Koujirou SHIBUYA Shintaro YAMAMICHI Masaya KAWANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/12/01
Vol. E92-C  No. 12  pp. 1512-1522
Type of Manuscript:  PAPER
Category: Electronic Components
Keyword: 
three-dimensional package, inter-chip connections, wide-band communication, fine interposer, bump, interconnection, 
 Summary | Full Text:PDF