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IEICE Trans

Shintaro NAKAMURA

Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor
Shintaro NAKAMURA Fujihiko MATSUMOTO Pravit TONGPOON Yasuaki NOGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1  pp. 128-131
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
CMOS, analog integrated circuits, transconductors, linear circuits, low noise, 
 Summary | Full Text:PDF