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IEICE Trans

Shinobu NAGAYAMA

Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2024/08/01
Vol. E107-D  No. 8  pp. 922-929
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: 
Keyword: 
symmetric functions, multiple-valued functions, functional decomposition, decision diagrams, 
 Summary | Full Text:PDF
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/08/01
Vol. E100-D  No. 8  pp. 1583-1591
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
index generation functions, linear decomposition, incompletely specified functions, balanced decision tree, content-addressable memory, logic design, heuristic, 
 Summary | Full Text:PDF
On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER Mitchell A. THORNTON Theodore W. MANIKAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2234-2242
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
minimization algorithm of the number of edges, EVMDDs, grouping variables for optimization of decision diagrams, multi-state systems, system analysis using decision diagrams, 
 Summary | Full Text:PDF
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2059-2067
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
two-variable numeric function generators (NFGs), edge-valued multiple-valued decision diagrams (EVMDDs), edge-valued binary decision diagrams (EVBDDs), graph-based representation of numeric functions, programmable memory-based architecture, 
 Summary | Full Text:PDF
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2752-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
edge-valued binary decision diagrams (EVBDDs), recursive segmentation, piecewise polynomial approximation, numerical function generators (NFGs), programmable architecture, 
 Summary | Full Text:PDF
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3510-3518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA, 
 Summary | Full Text:PDF
A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascade, LUT ring, multiple-output function, reconfigurable logic, programmable logic device, 
 Summary | Full Text:PDF
Area-Time Complexities of Multi-Valued Decision Diagrams
Shinobu NAGAYAMA Tsutomu SASAO Yukihiro IGUCHI Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5  pp. 1020-1028
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
decision diagrams, the number of nodes, area-time complexity, randomly generated function, representation of logic functions, 
 Summary | Full Text:PDF
Compact Representations of Logic Functions Using Heterogeneous MDDs
Shinobu NAGAYAMA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3168-3175
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
heterogeneous MDD, ROBDD, FBDD, APL, memory size, 
 Summary | Full Text:PDF