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IEICE Trans

Shinji HIRAMATSU

A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 818-824
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory, NAND, folded bit line verify read, charge pump, 
 Summary | Full Text:PDF