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IEICE Trans

Shinji FURUICHI

Pre-Route Power Analysis Techniques for SoC
Takashi YAMADA Takeshi SAKAMOTO Shinji FURUICHI Mamoru MUKUNO Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3  pp. 686-692
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoC, power analysis, gate-level, custom wire load model, 
 Summary | Full Text:PDF