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IEICE Trans

Shin-ichi ISHIDA

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1620-1628
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
100-Gbps Ethernet, network processor, cache, network traffic, low power, 
 Summary | Full Text:PDF
Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router
Michitaka OKUNO Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
router, Ethernet, packet-processing engine, network processor, cache-based packet-processing engine, 
 Summary | Full Text:PDF