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IEICE Trans

Shigeyuki OKADA

A Single-Chip JPEG2000 Encode Processor Capable of Compressing D1-Images at 30 frames/s without Tile Division
Hideki YAMAUCHI Shigeyuki OKADA Kazuhiko TAKETA Tatsushi OHYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4  pp. 448-456
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
JPEG2000, wavelet, system LSI, image compression, multimedia, 
 Summary | Full Text:PDF