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IEICE Trans

Shigeru ITO

On Fault Testing for Reversible Circuits
Satoshi TAYU Shigeru ITO Shuichi UENO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12  pp. 2770-2775
Type of Manuscript:  PAPER
Category: Complexity Theory
Keyword: 
3-SAT, CNOT gate, complete test set, fault testing, NP-complete, reversible circuit, stuck-at fault, test vector, 
 Summary | Full Text:PDF