Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 56

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 212

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 304

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 323
IEICE Trans

Shigemi KASHIMA

Timing Verification of Logic Circuits with Combined Delay Model
Shinji KIMURA Shigemi KASHIMA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10  pp. 1230-1238
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verification, computer aided design, logic simulation, 
 Summary | Full Text:PDF