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IEICE Trans

Satoshi YOKOTA

Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA Satoshi YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1749-1754
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description language, test suites, validation, CAD, 
 Summary | Full Text:PDF
Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
Satoshi YOKOTA Hiroyuki KANBARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1742-1748
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description language, conformance test, logic synthesis, UDL/I, 
 Summary | Full Text:PDF