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IEICE Trans

Satoshi SHIBATANI

A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays
Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3  pp. 506-513
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
multilayer routing, layout, CAD, VLSI, 
 Summary | Full Text:PDF
Synthesis of Testable Sequential Circuits with Reduced Checking Sequences
Satoshi SHIBATANI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7  pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequential circuit, design for testability, automated logic synthesis, checking sequence, state assignment, 
 Summary | Full Text:PDF